There is no consistent definition of a speed grade for all devices. Even for Xilinx, speed grades mean different things depending on if you are referring to a FPGA or a CPLD. For CPLDs, speed grades represent the time it takes for logic to go through the device (eg. in <= out). So a -10 device means that the device is guaranteed to send a signal from an input pin thru to an output pin in under 10 nS. So for CPLDs, the lower the number, the faster the part is. This is standard for CPLDs across all vendors so this can be used for device comparison purposes.
However for FPGAs, they don't use the same definition for speed grade. Originally speed grades for FPGAs represented the time through a look up table but now the speed grade doesn't actually repesent a timing path. I am not sure if it is the same for other vendors, but for Xilinx FPGAs higher numbers are faster. Each speed grade increment is ~15% faster than the one before it. So a -5 is 10% faster than a -4 speed grade.
Arthur
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Jasper,
As Arthur indicated, it is a relative term that is really dependent on the specific family:
-for CPLDs, it is generally pin-to-pin delays in nanoseconds (lower # = faster)
-for old Xilinx FPGAs (pre-Virtex), lower # was faster
-for modern (Virtex and later) FPGAs, the higher # is faster.
The speed grade influences a variety of timing paramters in the FPGA, including fabric (slice), multiplier/DSP48x, BlockRAM, I/O, and other resources parameters.
You really need to consult the specific datasheet to see specific details for timing based on associated speed grades.
For example, Virtex-4 speed grades are -10 (slowest), -11, and -12 (fatest)
Virtex-5 spede grades are -1 (slowest), -2, and -3 (fastest)
There is no correlation between these numbers. It is really a relative metric of performance within a specific family.
Cheers,
bt
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