两个时钟域的interface问题

By Rui Chen
Interfacing the two clock domains
Problem formulation
The two(or multiple) synchronous systems at different clock frequencies want to interface to each other.

Intuitive definition for asynchronous
The two clock domains are considered to asynchronous to each other when it meets:
1. different frequencies
2. same freq but different phase angle

Problems introduced when considering the interface:
1. setup and hold time violation
2. meta-stability
3. unreliable data transfer

reference: asic world

Possible solution from Lecture 10 of BlueSpec docs, while 2 and 4 matches with the solutions given by asic-world:
When interfacing the two clock domains, the intuitive solution is to introduce the synchronizer. According to lecture 10 ppt, the synchronizers can be divided into the following seven categories(also depicted in Appendix C.8 of reference guide):

1. 2-flop synchronizer
2. Pulse Synchronizer
3. Word Synchronizer
4. FIFO Synchronizer
5. Asynchronous RAM
6. Null Synchronizer
7. Reset Synchronizer

article: Multiclock designs in FPGA

In this article, the five specific problems are addressed:

1. Meta-stability(also has a vivid doc in asic-world) 

2. Reset synchronization
3. Glitch elimination across clock domain boundaries
4. Inadequate hold times for receiving clock domains
5. Loss of correlation among signals crossing clock domains

A solution: Clock intent verification

For more info, search with multiclock design or multiple clock design

Synthesis and Scripting Techniques for Designing MultiAsynchronous Clock Designs
very useful article try to address the problems in the field.
SUNG 3rd place, very competitive
The papers at SunBurst website are also good ref for design: Check them out