enum的翻译

By Rui Chen

VHDL 与systemc在enum的定义上有很大的不同。

VHDL-ref
Important Notes

• It is illegal to define an enumeration type with a range.
• It is assumed that the values are defined in ascending order. For this reason it is recommended to order the literals in such a way that the default value is the first one (it is referred to through the attribute 'left').
• Objects of enumeration types are typically synthesizeable.

所以，VHDL的